Japanese Patent Laid-Open No. 2001-45375 discloses a solid-state image sensing apparatus in which two pairs of external accumulation capacitors are arranged on a vertical output line 8 connected to pixels on each column in a pixel array in which a plurality of pixels are arranged in directions along the row and column, as shown in FIG. 1 of Japanese Patent Laid-Open No. 2001-45375. In this solid-state image sensing apparatus, external accumulation capacitors CTN2, CTS2, CTN1, and CTS1 are connected to the vertical output line 8 via MOS transistors 9 to 12, and horizontal output lines via MOS transistors 18, 17, 16, and 15. The MOS transistors 18 and 17 and the MOS transistors 16 and 15 are turned on/off by two horizontal transfer control lines 24 and 25, respectively.
In a period TH1 shown in FIG. 2 of Japanese Patent Laid-Open No. 2001-45375, the horizontal transfer control lines 24 of respective columns are sequentially activated to sequentially turn on the MOS transistors 18 and 17 of the respective columns, as represented by a waveform HSRC. In response to this, the signals of pixels on the (n−1)th row that are accumulated in the external accumulation capacitors CTN2 and CTS2 of the respective columns are sequentially transferred to a differential amplifier 21 via the horizontal output line. During a period T1 in the period TH1, φRES1 changes to high level to reset the stray capacitance of the gate of an amplifier 6 in each pixel on the (n)th row. During a period T2 in the period TH1, φTN1 changes to high level to transfer the signal of a noise component from each pixel on the (n)th row to the external accumulation capacitor CTN1 via the vertical output line 8. The external accumulation capacitor CTN1 holds the transferred signal. During a period T3 in the period TH1, φTX1 changes to high level to transfer photocharges stored in a photoelectric conversion element 2 of each pixel on the (n)th row to the stray capacitance of the gate of the MOS transistor via a MOS transistor 3. During a period T4 in the period TH1, φTS1 changes to high level to transfer the signal of the ‘photocharge component+noise component’ from each pixel on the (n)th row to the external accumulation capacitor CTS1 via the vertical output line 8. The external accumulation capacitor CTS1 holds the transferred signal.
According to Japanese Patent Laid-Open No. 2001-45375, a signal can be read out from a pixel during the horizontal transferring period. Thus, one horizontal scanning period can be fully used for the horizontal transferring period.
Japanese Patent Laid-Open No. 2001-45378 discloses a solid-state image sensing apparatus in which a vertical shift register VSR scans a row selection line connected to pixels on each row in a pixel array in which a plurality of pixels ‘a11’ to ‘b23’ are arranged in directions along the row and column, as shown in FIG. 1 of Japanese Patent Laid-Open No. 2001-45378. In this solid-state image sensing apparatus, accumulation units 1 and 2 are respectively connected to the two ends of a vertical signal line connected to pixels on each column of the pixel array.
In a period (‘transfer a’) during which TXa changes to high level, the vertical shift register VSR transfers the signals of pixels ‘a11’ to ‘a13’ on an odd-numbered row of the pixel array to the accumulation unit 1, as shown in FIG. 2 of Japanese Patent Laid-Open No. 2001-45378. In a period (‘transfer b’) during which TXb changes to high level, the vertical shift register VSR transfers the signals of pixels ‘b11’ to ‘b13’ on an even-numbered row of the pixel array to the accumulation unit 2. Parallel to this operation (‘transfer b’) of the vertical shift register VSR, a horizontal shift register HSR1 sequentially outputs the signals of the pixels ‘a11’ to ‘a13’ as OUT1 from the accumulation unit 1. Upon the lapse of a predetermined period (completion of ‘transfer b’) after the horizontal shift register HSR1 starts this operation, a horizontal shift register HSR2 sequentially outputs the signals of the pixels ‘b11’ to ‘b13’ as OUT2 from the accumulation unit 2 parallel to the operation of the horizontal shift register HSR1.
According to Japanese Patent Laid-Open No. 2001-45378, signals of two rows can be independently transferred to the two accumulation units in a given horizontal scanning period. A long readout period after transfer can be ensured, suppressing the readout operation frequency low.
In Japanese Patent Laid-Open No. 2001-45375, the solid-state image sensing apparatus has one signal transferring path (for pixels of one row) extending from the pixel array to the differential amplifier 21. The image sensing apparatus has a limit on shortening the total readout period from the pixel array to the differential amplifier 21.
According to Japanese Patent Laid-Open No. 2001-45378, the horizontal transfer operation OUT1 to transfer signals from the accumulation unit 1 to a differential amplifier D1 cannot be done in a period (‘transfer a’) during which the signals of the pixels ‘a11’ to ‘a13’ on an odd-numbered row are transferred to the accumulation unit 1, as shown in FIG. 2 of Japanese Patent Laid-Open No. 2001-45378. Also, the horizontal transfer operation OUT2 to transfer signals from the accumulation unit 2 to the other differential amplifier cannot be performed in a period (‘transfer b’) during which the signals of the pixels ‘b11’ to ‘b13’ on an even-numbered row are transferred to the accumulation unit 2. This image sensing apparatus includes two accumulation units and two differential amplifiers arranged for pixels of two rows. However, signal transfer from one accumulation unit to one differential amplifier and signal transfer from the other accumulation unit to the other differential amplifier need to start with a delay equal to or longer than the period of ‘transfer a’ or ‘transfer b’. This makes it difficult to shorten the total readout period from the pixel array to a plurality of differential amplifiers.